On Sat, May 19, 2007 at 11:15:01AM -0700, William Lee Irwin III wrote:
Of course smaller is smaller ;) Why would that make the cache cost
argument specious?
I don't really know what you mean by this, or what part of my cache cost
argument you disagree with...
I think it is that you could construct mem_map access patterns, without
specifically looking at alignment, where a 56 byte struct page would suffer
about 75% more cache misses than a 64 byte aligned one (and you could also
get about 12% fewer cache misses with other access patterns).
I also think the kernel's mem_map access patterns would be more on the
random side, so overall would result in significantly fewer cache misses
with 64 byte aligned pages.
Which part do you disagree with?
The issue is that userspace can DOS or crash the kernel by deliberately
overflowing count or mapcount.
Really? 64-bit architectures can already use about maybe 16 or 32 more
page flag bits than 32-bit architectures, and I definitely do not want
to increase the size of 32-bit struct page, so I think this wouldn't
work.
Don't get too hung up on the page->virtual thing. I'll send another
patch with atomic_t/atomic_long_t conversion.
I don't know what your 32 + PAGE_SHIFT calculation is for, but yes you
can wrap these counters from userspace on 64-bit architectures.
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