But hardware PC boards don't do anything as remotely complicate as
changing the semantics required for correctness in you MMU
implementation. There might be some weird MTRR and caching things,
which are a property of the architecture, and which all modern boards
have in common. You don't have completely diverse implementation
properties like shadow vs direct vs native page tables. Or hardware
virtualization vs direct CPL raised execution. You simply can't test
this diversity by making an educated guess, because in this case,
something will always be omitted. The test matrix has to be raised, and
if that is a problem, the burden of proper testing shifted onto the
manufacturers, just as you would with some new PC board or new
architecture that wanted to be Linux friendly but was radically
different in some way.
Zach
-