On 2/6/07, Grant Grundler <grundler@parisc-linux.org> wrote:i think probably, Linux is causing it to run again .. ? According to the information i have on this device .. Configuration Register 00H : Device_ID / Vendor_ID Register Bit [31:16] R Device_ID Device ID = 16'h4e35 Bit [15:0] R Vendor_ID Vendor ID = 16'h1822 Configuration Register 04H : Status / Command Register Bit 31 R Detpar_rpt Detect Parity Report Bit 30 W/R System_err Indicate System Error Bit 29 R Master_abort Indicate Master Abort Bit 28 R Target_abort Indicate Target Abort Bit [27:25] Default = 3'b001 Bit 24 R Datapar_rpt Data Parity Report Bit [23:20] Default = 4'b0000 Bit [19:16] Default = 4'b0000 Bit [15:9] Default = 7'h0 Bit 8 W/R Pci_serr_en PCI system error enable Bit 7 Default = 1'b0 Bit 6 W/R Pci_perr_en PCI parity error enable Bit [5:3] Default = 3'h0 Bit 2 W/R Pci_master_en PCI master mode enable Bit 1 W/R Pci_target_en PCI target mode enable Bit 0 Default = 1'b0 Configuration Register 08H : Class_Code / Revision_ID Register Bit [31:8] R Class_Code Class_Code = 24'h048000 Bit [7:0] R Revision_ID Revision_ID = 8'h01 Configuration Register 0CH : Latency Timer Register Bit [31:16] Default = 16'h0 Bit [15:11] W/R Pci_lat_timer Indicate PCI latency timer Bit [10:8] Default = 3'h0 Bit [7:0] Default = 8'b0 Configuration Register 10H : Base_Address / Memory&Prep Register Bit [31:12] W/R Pci_base_addr Indicate PCI Base Address Bit [31:0] R Default = 12'h008 Configuration Register 2CH : I2C Subsystem_ID / Subsystem_Vendor_ID Register Bit [31:0] W/R I2c_ssid_ssvid Indicate I2C subsystem_ID / subsystem_vendor_ID Configuration Register 38H : Test PCI Connection Register Bit [31:0] W/R Test_pci_conn Indicate to test PCI connection Configuration Register 3CH : Max_Latency / Min_Gnt / Int_Pin / Int_Line Register Bit [31:24] W Max_lat Default = 8'hFF Bit [23:16] W Min_gnt Default = 8'h08 Bit [15:8] W Int_pin Default = 8'h01 Bit [7:0] W/R Int_line Indicate interrupt line AFAIK, the device does 32 bit DMA, but it is not completely hardware driven DMA. it just uses a RISC core which just jumps to the pointer allocated in software. The other devices using the same chip, works that way. thanks, manu -
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