> > 2.15.2 PCI Express* Legacy INTx Support and Boot Interrupt
> >
http://download.intel.com/design/chipsets/datashts/30262802.pdf
>
> Ouch. And this kind of thing isn't exactly uncommon.
>
> However if we have the irqs also disabled in the i8259 we should
> be safe from actually receiving this interrupt (even if it generates
> bus traffic), and when we enable the irq since it is level triggered
> we should still get an interrupt message.
>
> It isn't immediately obvious where the i8259 irq enable/disable
> happens. So i"m having trouble auditing that bit of code.
>
> Plus we can get very strange things like the irq number changing
> and the sharing rules being different when going through the i8259.
> So irqN may be irqM when going through the i8259.
>
> As long as we aren't using anything on the i8259 including the timer
> in ExtINT mode we can disable every interrupt pin and not worry about
> interrupts from that source.
