On Wed, 26 Dec 2007 00:09:57 +0100

Pavel Machek  wrote:
> On Sat 2007-12-22 12:09:59, Arjan van de Ven wrote:

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> > On Tue, 18 Dec 2007 17:06:24 +0000

> > memtest86+ does various magic to basically bypass the caches (by

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> > disabling them ;-)... Doing that in a live kernel situation, and

> > from userspace to boot...... that's... and issue.

>

> Are you sure? I always assumed that memtest just used patterns bigger

> than L1/L2 caches...

that's... not nearly usable or enough. Caches are relatively smart

about things like use-once.... and they're huge. 12Mb today. You'd need

patterns bigger than 100Mb to get even close to being reasonably

confident that there's nothing left.
> ... and IIRC my celeron testing confirmed it, if

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> I disabled L2 cache in BIOS, memtest behave differently.

>

> Anyway, if you can do iopl(), we may as well let you disable caches,

> but you are right, that will need a kernel patch.

and a new syscall of some sorts I suspect; "flush all caches" is a ring

0 operation (and you probably need to do it in an ipi anyway on all

cpus)
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