On Mon, 2007-12-10 at 15:47 +0000, Ralf Baechle wrote:
quoted text
> 
> 
> > 0000:00:09.1 IDE interface: VIA Technologies, Inc.
> > VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06)
> > (prog-if 8a [Master SecP PriP])
> >         Flags: bus master, fast Back2Back, medium devsel, latency 64
> >         I/O ports at 1820 [size=16]
> 
> And that's lspci -v -b:
> 
> > 0000:00:09.1 IDE interface: VIA Technologies, Inc.
> > VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06)
> > (prog-if 8a [Master SecP PriP])
> >         Flags: bus master, fast Back2Back, medium devsel, latency 64
> >         I/O ports at 10001820
> 
> So the IDE controller already seems to be in native mode?
> 

No, native mode is 5 not A in the low 4 bits of progif.

You need to be a bit careful about those VIA, I remember having issues
on Pegasos where we left it in legacy mode. It think the problem is that
even when switched, the IRQ routing might be done based on some other
setting in the chipset, possibly a strap. But that's nothing you can't
deal with an appropriate quirk in the arch code.

Also, double check the level/edge setting of the interrupts as it can be
different between legacy and native (native is level low, legacy is
rising edge).

I'm surprised however that one would use such a legacy southbridge on a
platform that can't issue low IO ports, that doesn't seem to make sense
to me ... there's a whole lot of things on this such as the 8259 PIC
etc.. that can only be addressed via low IOs, unless the ISA space can
be somewhat remapped ?

Ben.


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