Mikael Pettersson wrote:
quoted text
> 
> Maybe not. I had a look in Intel's SDM Vol3, and the
> section "switching to protected mode" specifies that
> a move to %cr0 that sets PE should immediately be
> followed by a far jmp or call. They write that "random
> failures can occur if other instructions exist between
> [the move to %cr0] and [the far jmp/call]". The current
> version of pmjump.S does exactly that: it executes
> a bunch of moves to segment registers in that window.
> 
> (Section 9.9.1 in the Sept. 2005 revision I have in
> front of me.)
> 
> Similarly, section "serializing instructions" writes
> that a move to %cr0 that enables or disables paging
> should be followed by a jump. They write that this isn't
> required in P4 or P6 family processors, but is required
> for compatibility with other ia32 processors. Reading
> between the lines, they imply that older ia32 processors
> don't treat %cr0 writes as completely serializing.
> 
> (Section 7.4 in the Sept. 2005 revision.)
> 

The problem is that Intel has a tendency to exaggerate in their 
documentation; in particular, they tend not to remove restrictions that 
are long-since obsolete.  However, it sounds like you have actually 
found a CPU for which this restriction is motivated.

	-hpa
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