On Tue, Nov 27, 2007 at 03:24:35PM -0800, Ben Woodard wrote:
quoted text
> Andi Kleen wrote:
>>> Are we putting the system back in PIC mode or virtual wire mode? I have
>>> not seen systems which support PIC mode. All latest systems seems
>>> to be having virtual wire mode. I think in case of PIC mode, interrupts
>>
>> Yes it's probably virtual wire. For real PIC mode we would need really
>> old systems without APIC.
>>
>>> can be delivered to cpu0 only. In virt wire mode, one can program IOAPIC
>>> to deliver interrupt to any of the cpus and that's what we have been
>>
>> The code doesn't try to program anything specific, it just restores the state
>> that was left over originally by the BIOS.
>>
>
> So if the BIOS originally left the IOAPIC in a state where the timer 
> interrupts were only going to CPU0 then by restoring that state we could be 
> bringing this problem upon ourselves when we restore that state.
>

Hi Ben,

Apart from restoring the original state (Bring APICS back to virtual wire
mode), we also reprogram IOAPIC so that timer interrupt can go to crashing
cpu (and not necessarily cpu0). Look at following code in disable_IO_APIC.

                entry.dest.physical.physical_dest =
                                        GET_APIC_ID(apic_read(APIC_ID));

Here we read the apic id of crashing cpu and program IOAPIC accordingly.
This will make sure that even in virtual wire mode, timer interrupts
will be delivered to crashing cpu APIC.

I think we need to go deeper and compare the state of system (APICS,
timer etc) during normal boot and kdump boot and see where is the
difference. This is how I solved some of the timer interrupt related
issues in the past.

Thanks
Vivek
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