Mathieu Desnoyers wrote:
quoted text
> Immediate Values - x86 Optimization
> 
> x86 optimization of the immediate values which uses a movl with code patching
> to set/unset the value used to populate the register used as variable source.
> 
> Changelog:
> - Use text_poke_early with cr0 WP save/restore to patch the bypass. We are doing
>   non atomic writes to a code region only touched by us (nobody can execute it
>   since we are protected by the immediate_mutex).
> - Put immediate_set and _immediate_set in the architecture independent header.
> - Use __PLACEHOLDER__0_ instead of %2 with (0) operand.
> - Add x86_64 support, ready for i386+x86_64 -> x86 merge.
> - Use asm-x86/asm.h.
> 
> Ok, so the most flexible solution that I see, that should fit for both
> i386 and x86_64 would be :
> 1 byte  : "=Q" : Any register accessible as rh: a, b, c, and d.
> 2, 4 bytes : "=R" : Legacy register—the eight integer registers available
>                  on all i386 processors (a, b, c, d, si, di, bp, sp). 8
> bytes : (only for x86_64)
>           "=r" : A register operand is allowed provided that it is in a
>                  general register.
> That should make sure x86_64 won't try to use REX prefixed opcodes for
> 1, 2 and 4 bytes values.
> 

I just had a couple of utterly sick ideas.

Consider this variant (this example is for a 32-bit immediate on x86-64, 
but the obvious macroizations apply):

	.section __discard,"a",@progbits
1:	movl $0x12345678,%r9d
2:
	.previous

	.section __immediate,"a",@progbits
	.quad foo_immediate, (3f)-4, 4
	.previous
	
	.org . + ((-.-(2b-1b)) & 3), 0x90
	movl $0x12345678,%r9d
3:


The idea is that the instruction is emitted into a section, which is 
marked DISCARD in the linker script.  That lets us actually measure the 
length, and since we know the immediate is always at the end of the 
instruction... done!

	-hpa

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