Cc: Linux Kernel list <linux-kernel@...>, Felipe Balbi <felipebalbi@...>, Bill Gatliff <bgat@...>, Haavard Skinnemoen <hskinnemoen@...>, Andrew Victor <andrew@...>, Tony Lindgren <tony@...>, Jean Delvare <khali@...>, Kevin Hilman <khilman@...>, Paul Mundt <lethal@...>, Ben Dooks <ben@...>
We "can" do most anything. What would that improve though?
Each irq_chip handles multiple IRQs ... just like this patch
has each gpio_chip handling multiple GPIOs. (Not that I think
GPIO code should closely model IRQ code; they need to address
very different problems.)
I can't tell what you intend to suggest as a "per-GPIO" data
structure; since I can think of at least three different ways
to do such a thing, you should be more concrete. I'd think it
should be in *addition* to a gpio_chip structure though.
The can_sleep value is a per-controller thing. The other bits are
indeed per-GPIO.
So do you mean a structure with two bits, plus a pointer to a
gpio_chip, plus likely other stuff (what?) to make it work?
What would the hot-path costs be (for getting/setting values of
an on-chip GPIO)?
Why should holes (in the GPIO number sequence) be a problem? In
this code, they don't cost much space at all. They'd cost more
if there were a per-GPIO structure though...
The only downside of GPIOS_PER_CHIP that I know of right now
is that it complicates mixing gpio bank sizes; it's a ceiling,
some controllers would allocate more than they need. The
upside of that is efficiency, and a closer match to how
underlying hardware works.
Of course, GPIOS_PER_CHIP *could* be decoupled from how the
table of gpio_chip pointers is managed. If the table were to
group GPIOs in units of 8, a gpio_chip with 32 GPIOs could
take four adjacent entries while an 8-bit GPIO expander could
take just one. That'd be a very easy patch, supporting a more
dense allocation of GPIO numbers... although it would increase
static memory consumption by typically NR_GPIOS/4 pointers.
I'd say "return chips[gpio / ARCH_GPIOS_PER_CHIP]" already meets
both criteria!
There's also "efficient" to consider; this way doesn't cost much
memory or add levels of indirection (compared to most platforms,
which already use a similar array).
Why would per-GPIO locking be needed though? Look again...
The locking is there fundamentally because gpio_chip structures
may need to be unregistered; that's not a per-gpio issue.
Even when a gpio is marked in chip->requested under that lock,
that's part of ensuring that the unregistration is prevented so
long as the GPIO is in active use.
Plus, fine grained locking is rarely a good idea; it normally
increases locking overhead by involving multiple locks. Only
add extra locks if a single lock sees too much contention; and
even then, only if that contention can't be removed by using a
smarter design.
- Dave
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