On Monday 08 October 2007 14:39:33 Ingo Molnar wrote:I did that .text reduction only to make up for the text increase from the other patch. Your approach is asking for keeping them both in a single patch next time, which surely cannot be what you really want. Ok, but I trust I have at least 0.5kb bloat budget for future changes now. That's like saying all optimizations are a workaround for lack of hardware with infinite IPC. Yes sure. But that doesn't seem like a very fruitful way to reason. Besides even on CPUs with indirect branch predictor it is probably a win -- they tend to have much less memory to store indirect branch prediction (requires an address) than for conditional jumps (requires just a bit) The difference is that the VFS always did indirect calls; but the scheduler didn't. And again it's much less clear for the VFS in general what are the common paths. To do it fully generic would probably require a JIT and reoptimization at run time -- i don't think that's a path we should go. But if generic solutions are not possible doing it for important special cases where it happens to be possible is certainly a valid approach. But given that I couldn't come up with clear numbers it's reasonable to not apply it yet. I'll try to come up with some better way to measure this. -Andi -
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| Greg Kroah-Hartman | [PATCH 002/196] Chinese: rephrase English introduction in HOWTO |
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git: | |
| Gerrit Renker | [PATCH 27/37] dccp: Integration of dynamic feature activation - part 2 (server side) |
| Jarek Poplawski | [PATCH] pkt_sched: Destroy gen estimators under rtnl_lock(). |
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| Jeff Garzik | Re: [bug?] tg3: Failed to load firmware "tigon/tg3_tso.bin" |
