On Thu, Oct 04, 2007 at 07:22:58AM +0200, Nick Piggin wrote:

 > -#ifdef CONFIG_X86_OOSTORE
 > -/* Actually there are no OOO store capable CPUs for now that do SSE, 
 > -   but make it already an possibility. */
 > -#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 > -#else
 > -#define wmb()	__asm__ __volatile__ ("": : :"memory")
 > -#endif
 > -
 >  #ifdef CONFIG_SMP
 >  #define smp_mb()	mb()
 >  #define smp_rmb()	rmb()
 > -#define smp_wmb()	wmb()
 > +#ifdef CONFIG_X86_OOSTORE
 > +# define smp_wmb() 	wmb()
 > +#else
 > +# define smp_wmb()	barrier()
 > +#endif

The only vendor that ever implemented OOSTOREs was Centaur, and they
only did in the Winchip generation of the CPUs.  When they dropped it
from the C3, I asked whether they intended to bring it back, and the
answer was "extremely unlikely".

So we can probably just drop that "just in case" clause above, and just
do..

 #define smp_wmb()  barrier()


	Dave

-- 
http://www.codemonkey.org.uk
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