On Wed, 3 Oct 2007, Pekka Enberg wrote:Not unless memtest uses non-temporal stores with the same (or similar) access patterns. The thing is, the CPU cache hides a *lot* of activity from the chipset, and changes the access patterns radically. With normal cached accesses, you'd normally see just the "fill cacheline" and "write out cacheline" pattern. With movnt, you'd see non-cacheline accesses to memory. If the chipset was tested under mostly normal loads, the movnt cases have been getting a lot less coverage. Now, I do agree that it certainly *can* be a CPU bug too. I doubt it, though. I'd check the power supply (brownouts cause random corruption, and it might have a "peak power pattern" thing to it), and it's worth re-seating any DIMM's etc. And it's definitely worth going into the BIOS setup screen and making sure that nothing is even close to debatable (ie take RAM timings down to non-aggressive levels, make sure bus frequencies and multipliers are not even close to borderline, etc etc). Linus -
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| Greg Kroah-Hartman | [PATCH 005/196] Chinese: add translation of SubmittingDrivers |
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git: | |
| Gerrit Renker | [PATCH 03/37] dccp: List management for new feature negotiation |
| Frans Pop | svc: failed to register lockdv1 RPC service (errno 97). |
| David Miller | Re: [PATCH] pkt_sched: Destroy gen estimators under rtnl_lock(). |
| David Miller | [GIT]: Networking |
