On Friday 26 October 2007 00:49:42 Nick Piggin wrote:Poor code is better than broken code I would say. Besides the cross CPU synchronization paths are likely dominated by cache misses anyways; it's unlikely they're actually limited by the core CPU. So it'll probably not matter all that much if the code is poor or not. But it's all theoretical for now. I checked my kernel for "adc" at least (for the trylock/++ pattern) and couldn't find any (in fact all of them were in data the compiler thought to be code). That was not a allyesconfig build, so i missed some code. For cmov it's at first harder because they're much more frequent and cmov to memory is a multiple instruction pattern (the instruction does only support memory source operands). Luckily gcc doesn't know the if (x) mem = a; => ptr = cmov(x, &a, &dummy); *ptr = a; transformation trick so I don't think there are actually any conditional stores on current x86. It might be a problem on other architectures which support true conditional stores though (like IA64 or ARM) Also I'm not sure if gcc doesn't know any other tricks like the conditional add using carry, although I cannot think of any related to stores from the top of my hat. Anyways, if it's only conditional add if we ever catch such a case it could be also handled with inline assembly similar to local_inc() -Andi -
| Tarkan Erimer | Re: Dual-Licensing Linux Kernel with GPL V2 and GPL V3 |
| Greg KH | [GIT PATCH] driver core patches against 2.6.24 |
| Ingo Molnar | [git pull] x86 arch updates for v2.6.25 |
| Anton Salikhmetov | [PATCH -v8 2/4] Update ctime and mtime for memory-mapped files |
git: | |
| Patrick McHardy | Re: [GIT]: Networking |
| Jarek Poplawski | [PATCH] pkt_sched: Destroy gen estimators under rtnl_lock(). |
| Gerrit Renker | [PATCH 16/37] dccp: API to query the current TX/RX CCID |
| Andrew Morton | Re: [BUG] New Kernel Bugs |
