On Tue, 2 Oct 2007, Andi Kleen wrote:
quoted text
> > Agreed.
> > 
> > I just got a x8664-hrt report, where I found the following oddity:
> > 
> >  0:       1197     172881   IO-APIC-edge      timer
> > 
> > That's one of those infamous AMD C1E boxen. Strange, all my systems have 
> > IRQ#0 on CPU#0 and nowhere else. Any idea ?
> 
> Hmm, in lowestpriority mode it would be possible that the APIC changes
> the CPU to #1 once; but IRQ 0 is always set to fixed mode. Also even 
> if that happens you should have them all on 1.
> 
> Maybe the chipset is just ignoring the IO-APIC configuration in this case?
> 
> Is it always the same chipset? Is it seen on i386 too?
> 
> The problem is really that if this happens it's more than the NMI watchdog
> that is broken. If you don't run an additional APIC timer interrupt on CPU #0
> it's possible that CPU #0 won't schedule at all.
>
> The only workaround for chipsets ignoring IRQ affinity would be to keep
> track on which CPU irq 0 happens and then restart APIC timer interrupts
> on the others (or send IPIs) as needed. But that would be fairly ugly.

The clock events code does handle this already. The broadcast interrupt 
can come in on any cpu. It's just the nmi watchdog which would be affected 
by that.

	tglx
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