Re: LFENCE instruction (was: [rfc][patch 3/3] x86: optimise barriers)

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To: Nick Piggin <npiggin@...>
Cc: Arjan van de Ven <arjan@...>, Linux Kernel Mailing List <linux-kernel@...>
Date: Tuesday, October 16, 2007 - 8:30 pm

> > You already must not place any data structures into WC memory --- for 

I mean "in current kernel" (I checked it in 2.6.22)


You read wrong part of the include file. Really, it is 
(2.6.22,include/asm-i386/system.h):
#ifdef CONFIG_X86_OOSTORE
#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", 
X86_FEATURE_XMM)
#else
#define wmb()   __asm__ __volatile__ ("": : :"memory")
#endif

CONFIG_X86_OOSTORE is dependent on MWINCHIP3D || MWINCHIP2 || MWINCHIPC6
--- so on Intel and AMD, it is really just barrier().

So drivers can't assume that wmb() works on write-combining memory.


Because it is defined as __asm__ __volatile__ ("": : :"memory")

And WC memory can reorder writes (WB memory can't).



I mean this: wmb() assumes that the data to be ordered are not in WC 
memory. rmb() assumes that the data can be in WC memory (lfence is only 
useful on WC --- it doesn't have any effect on other memory types).

Mikulas
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Messages in current thread:
Re: LFENCE instruction (was: [rfc][patch 3/3] x86: optimise ..., Mikulas Patocka, (Tue Oct 16, 8:30 pm)
Re: LFENCE instruction, H. Peter Anvin, (Tue Oct 16, 11:42 am)
Re: LFENCE instruction, Mikulas Patocka, (Tue Oct 16, 5:25 pm)