This patchset includes two patches.
1. Checks for the MCA fetures as early as possible and signedness fixup.

2. Minor coding style cleanup.
-

MCG_CAP never reports a negative count of available error-reporting banks.

Therefore, make nr_mce_banks unsigned.

Check for MCE feature bit as early as possible and clean up the extra _MCE

checks in the various cpu init type functions per request from Thomas Gleixner.
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

---

 arch/x86/kernel/cpu/mcheck/k7.c  |    6 +-----

 arch/x86/kernel/cpu/mcheck/mce.c |   12 ++++++++++--

 arch/x86/kernel/cpu/mcheck/mce.h |    2 +-

 arch/x86/kernel/cpu/mcheck/p5.c  |    4 ----

 arch/x86/kernel/cpu/mcheck/p6.c  |    4 ----

 5 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/arch/x86/kernel/cpu/mcheck/k7.c b/arch/x86/kernel/cpu/mcheck/k7.c

index eef63e3..ad68cc9 100644

--- a/arch/x86/kernel/cpu/mcheck/k7.c

+++ b/arch/x86/kernel/cpu/mcheck/k7.c

@@ -72,13 +72,9 @@ void amd_mcheck_init(struct cpuinfo_x86 *c)

 	u32 l, h;

 	int i;
-	if (!cpu_has(c, X86_FEATURE_MCE))

-		return;

-

 	machine_check_vector = k7_machine_check;

 	wmb();
-	printk (KERN_INFO "Intel machine check architecture supported.\n");

 	rdmsr (MSR_IA32_MCG_CAP, l, h);

 	if (l & (1<<8))	/* Control register present ? */

 		wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);

@@ -97,6 +93,6 @@ void amd_mcheck_init(struct cpuinfo_x86 *c)

 	}
 	set_in_cr4 (X86_CR4_MCE);

-	printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",

+	printk (KERN_INFO "CPU%d: AMD K7 machine check reporting enabled.\n",

 		smp_processor_id());

 }

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c

index 34c781e..c7246cc 100644

--- a/arch/x86/kernel/cpu/mcheck/mce.c

+++ b/arch/x86/kernel/cpu/mcheck/mce.c

@@ -17,7 +17,7 @@

 #include "mce.h"
 int mce_disabled = 0;

-int nr_mce_banks;

+unsigned int nr_mce_banks;
 EXPORT_SYMBOL_GPL(nr_mce_banks);	/* non-fatal.o */
@@ -33,8 +33,16 @@ void fastcall (*machine_check_vector)(struct pt_regs *, long error_code) = u...
[ message continues ]

remove one indent level
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

---

 arch/x86/kernel/cpu/mcheck/mce.c |   40 +++++++++++++++++++-------------------

 1 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c

index c7246cc..e418c2f 100644

--- a/arch/x86/kernel/cpu/mcheck/mce.c

+++ b/arch/x86/kernel/cpu/mcheck/mce.c

@@ -45,26 +45,26 @@ void mcheck_init(struct cpuinfo_x86 *c)

 	}
 	switch (c->x86_vendor) {

-		case X86_VENDOR_AMD:

-			amd_mcheck_init(c);

-			break;

-

-		case X86_VENDOR_INTEL:

-			if (c->x86==5)

-				intel_p5_mcheck_init(c);

-			if (c->x86==6)

-				intel_p6_mcheck_init(c);

-			if (c->x86==15)

-				intel_p4_mcheck_init(c);

-			break;

-

-		case X86_VENDOR_CENTAUR:

-			if (c->x86==5)

-				winchip_mcheck_init(c);

-			break;

-

-		default:

-			break;

+	case X86_VENDOR_AMD:

+		amd_mcheck_init(c);

+		break;

+

+	case X86_VENDOR_INTEL:

+		if (c->x86==5)

+			intel_p5_mcheck_init(c);

+		if (c->x86==6)

+			intel_p6_mcheck_init(c);

+		if (c->x86==15)

+			intel_p4_mcheck_init(c);

+		break;

+

+	case X86_VENDOR_CENTAUR:

+		if (c->x86==5)

+			winchip_mcheck_init(c);

+		break;

+

+	default:

+		break;

 	}

 }
--

1.5.2.5
-