Most of these fixes were already submitted for old kernel versions, and were approved, but for some reason they never made it into the releases.  I've updated the changes for the 2.6.23 kernel and attached the resulting patch.  Because this is a consolidation of a couple old missed patches, it touches both Kconfigs and documentation texts.
Signed-off-by: Matt LaPlante <kernel1@cyberdogtech.com>

--
diff -ru a/arch/arm/Kconfig b/arch/arm/Kconfig

--- a/arch/arm/Kconfig	2007-10-09 16:31:38.000000000 -0400

+++ b/arch/arm/Kconfig	2007-10-09 17:32:13.000000000 -0400

@@ -848,7 +848,7 @@

 	help

 	  kexec is a system call that implements the ability to shutdown your

 	  current kernel, and to start another kernel.  It is like a reboot

-	  but it is indepedent of the system firmware.   And like a reboot

+	  but it is independent of the system firmware.   And like a reboot

 	  you can start any kernel with it, not just Linux.
 	  It is an ongoing process to be certain the hardware in a machine

diff -ru a/arch/avr32/Kconfig b/arch/avr32/Kconfig

--- a/arch/avr32/Kconfig	2007-10-09 16:31:38.000000000 -0400

+++ b/arch/avr32/Kconfig	2007-10-09 17:32:13.000000000 -0400

@@ -189,7 +189,7 @@
 endmenu
-menu "Power managment options"

+menu "Power management options"
 menu "CPU Frequency scaling"
diff -ru a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig

--- a/arch/blackfin/Kconfig	2007-10-09 16:31:38.000000000 -0400

+++ b/arch/blackfin/Kconfig	2007-10-09 17:32:13.000000000 -0400

@@ -458,85 +458,86 @@

 	bool "Locate interrupt entry code in L1 Memory"

 	default y

 	help

-	  If enabled interrupt entry code (STORE/RESTORE CONTEXT) is linked

-	  into L1 instruction memory.(less latency)

+	  If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked

+	  into L1 instruction memory. (less latency)
 config EXCPT_IRQ_SYSC_L1

-	bool "Locate entire ASM lowlevel excepetion / interrupt - Syscall and CPLB handler code in L1 Memory"

+	bool "Locate entire ASM lowlevel exception / inte...
[ message continues ]

Matt LaPlante wrote:
As a side note:  Submissions which touch multiple files are more

readable if prepended by the diffstat.  Thanks,

--

Stefan Richter

-=====-=-=== =-=- -=-=-

http://arcgraph.de/sr/

-

Hi Matt,
                         software
Thanks.
---

~Randy

-

On Tue, 9 Oct 2007 16:12:14 -0700
Thanks as always, Randy.  Fixes below...
--
diff -ru a/arch/arm/Kconfig b/arch/arm/Kconfig

--- a/arch/arm/Kconfig	2007-10-09 16:31:38.000000000 -0400

+++ b/arch/arm/Kconfig	2007-10-10 08:44:31.000000000 -0400

@@ -848,7 +848,7 @@

 	help

 	  kexec is a system call that implements the ability to shutdown your

 	  current kernel, and to start another kernel.  It is like a reboot

-	  but it is indepedent of the system firmware.   And like a reboot

+	  but it is independent of the system firmware.   And like a reboot

 	  you can start any kernel with it, not just Linux.
 	  It is an ongoing process to be certain the hardware in a machine

diff -ru a/arch/avr32/Kconfig b/arch/avr32/Kconfig

--- a/arch/avr32/Kconfig	2007-10-09 16:31:38.000000000 -0400

+++ b/arch/avr32/Kconfig	2007-10-10 08:44:31.000000000 -0400

@@ -189,7 +189,7 @@
 endmenu
-menu "Power managment options"

+menu "Power management options"
 menu "CPU Frequency scaling"
diff -ru a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig

--- a/arch/blackfin/Kconfig	2007-10-09 16:31:38.000000000 -0400

+++ b/arch/blackfin/Kconfig	2007-10-10 08:44:31.000000000 -0400

@@ -458,85 +458,86 @@

 	bool "Locate interrupt entry code in L1 Memory"

 	default y

 	help

-	  If enabled interrupt entry code (STORE/RESTORE CONTEXT) is linked

-	  into L1 instruction memory.(less latency)

+	  If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked

+	  into L1 instruction memory. (less latency)
 config EXCPT_IRQ_SYSC_L1

-	bool "Locate entire ASM lowlevel excepetion / interrupt - Syscall and CPLB handler code in L1 Memory"

+	bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"

 	default y

 	help

-	  If enabled entire ASM lowlevel exception and interrupt entry code (STORE/RESTORE CONTEXT) is linked

-	  into L1 instruction memory.(less latency)

+	  If enabled, the entire ASM lowlevel exception and interrupt entry code

+	  (STORE/RESTORE CONTEX...
[ message continues ]

Acked-by: Randy Dunlap <randy.dunlap@oracle.com>
Thanks, Matt.
--

~Randy

-