From: Peter Zijlstra <a.p.zijlstra@chello.nl> Date: Fri, 05 Oct 2007 22:32:00 +0200The other important bit is likely to generate a lot of DMA traffic such that the L2 cache bandwidth is getting used on the bus side by the PCI controller doing invalidations of both dirty and clean L2 cache lines as devices DMA to/from them. This will also be exercising the memory controller, further contending with the cpu when SLAB touches cold data structures. - To unsubscribe from this list: send the line "unsubscribe linux-fsdevel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
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