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From: Jarod Wilson <jarod@redhat.com> We don't actually need most of the register defines to build, and most of the ones we don't need aren't currently interesting. We'll leave a full copy of all of them in libcrystalhd's source, and only include what we need and/or think might be interesting in the driver. Signed-off-by: Jarod Wilson <jarod@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> --- drivers/staging/crystalhd/bcm_70012_regs.h |11542 ---------------------------- 1 files changed, 0 insertions(+), 11542 deletions(-) diff --git a/drivers/staging/crystalhd/bcm_70012_regs.h b/drivers/staging/crystalhd/bcm_70012_regs.h index b3b2557..6922f54 100644 --- a/drivers/staging/crystalhd/bcm_70012_regs.h +++ b/drivers/staging/crystalhd/bcm_70012_regs.h @@ -203,21 +203,6 @@ ***************************************************************************/ #define PCIE_TL_TL_CONTROL 0x00000400 /* TL_CONTROL Register */ #define PCIE_TL_TRANSACTION_CONFIGURATION 0x00000404 /* TRANSACTION_CONFIGURATION Register */ -#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00000408 /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ -#define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 0x0000040c /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 Register */ -#define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00000410 /* DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ -#define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 0x00000414 /* DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 Register */ -#define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC 0x00000418 /* DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC Register */ -#define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC 0x0000041c /* DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC Register */ -#define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC 0x00000420 /* READ_DMA_SPLIT_IDS_DIAGNOSTIC Register */ -#define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC 0x00000424 /* READ_DMA_SPLIT_LENGTH_DIAGNOSTIC Register */ -#define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC 0x0000043c /* XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC Register */ -#define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC 0x00000458 /* DMA_COMPLETION_MISC__DIAGNOSTIC Register */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC 0x0000045c /* SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC Register */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC 0x00000460 /* SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC Register */ -#define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC 0x00000464 /* SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC Register */ -#define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO 0x00000468 /* TL_BUS_NO_DEV__NO__FUNC__NO Register */ -#define PCIE_TL_TL_DEBUG 0x0000046c /* TL_DEBUG Register */ /**************************************************************************** @@ -225,47 +210,6 @@ ***************************************************************************/ #define PCIE_DLL_DATA_LINK_CONTROL 0x00000500 /* DATA_LINK_CONTROL Register */ #define PCIE_DLL_DATA_LINK_STATUS 0x00000504 /* DATA_LINK_STATUS Register */ -#define PCIE_DLL_DATA_LINK_ATTENTION 0x00000508 /* DATA_LINK_ATTENTION Register */ -#define PCIE_DLL_DATA_LINK_ATTENTION_MASK 0x0000050c /* DATA_LINK_ATTENTION_MASK Register */ -#define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000510 /* NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ -#define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000514 /* ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ -#define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000518 /* PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ -#define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG 0x0000051c /* RECEIVE_SEQUENCE_NUMBER_DEBUG Register */ -#define PCIE_DLL_DATA_LINK_REPLAY 0x00000520 /* DATA_LINK_REPLAY Register */ -#define PCIE_DLL_DATA_LINK_ACK_TIMEOUT 0x00000524 /* DATA_LINK_ACK_TIMEOUT Register */ -#define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD 0x00000528 /* POWER_MANAGEMENT_THRESHOLD Register */ -#define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG 0x0000052c /* RETRY_BUFFER_WRITE_POINTER_DEBUG Register */ -#define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG 0x00000530 /* RETRY_BUFFER_READ_POINTER_DEBUG Register */ -#define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG 0x00000534 /* RETRY_BUFFER_PURGED_POINTER_DEBUG Register */ -#define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT 0x00000538 /* RETRY_BUFFER_READ_WRITE_DEBUG_PORT Register */ -#define PCIE_DLL_ERROR_COUNT_THRESHOLD 0x0000053c /* ERROR_COUNT_THRESHOLD Register */ -#define PCIE_DLL_TL_ERROR_COUNTER 0x00000540 /* TL_ERROR_COUNTER Register */ -#define PCIE_DLL_DLLP_ERROR_COUNTER 0x00000544 /* DLLP_ERROR_COUNTER Register */ -#define PCIE_DLL_NAK_RECEIVED_COUNTER 0x00000548 /* NAK_RECEIVED_COUNTER Register */ -#define PCIE_DLL_DATA_LINK_TEST 0x0000054c /* DATA_LINK_TEST Register */ -#define PCIE_DLL_PACKET_BIST 0x00000550 /* PACKET_BIST Register */ -#define PCIE_DLL_LINK_PCIE_1_1_CONTROL 0x00000554 /* LINK_PCIE_1_1_CONTROL Register */ - - -/**************************************************************************** - * BCM70012_TGT_TOP_PCIE_PHY - ***************************************************************************/ -#define PCIE_PHY_PHY_MODE 0x00000600 /* TYPE_PHY_MODE Register */ -#define PCIE_PHY_PHY_LINK_STATUS 0x00000604 /* TYPE_PHY_LINK_STATUS Register */ -#define PCIE_PHY_PHY_LINK_LTSSM_CONTROL 0x00000608 /* TYPE_PHY_LINK_LTSSM_CONTROL Register */ -#define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER 0x0000060c /* TYPE_PHY_LINK_TRAINING_LINK_NUMBER Register */ -#define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER 0x00000610 /* TYPE_PHY_LINK_TRAINING_LANE_NUMBER Register */ -#define PCIE_PHY_PHY_LINK_TRAINING_N_FTS 0x00000614 /* TYPE_PHY_LINK_TRAINING_N_FTS Register */ -#define PCIE_PHY_PHY_ATTENTION 0x00000618 /* TYPE_PHY_ATTENTION Register */ -#define PCIE_PHY_PHY_ATTENTION_MASK 0x0000061c /* TYPE_PHY_ATTENTION_MASK Register */ -#define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER 0x00000620 /* TYPE_PHY_RECEIVE_ERROR_COUNTER Register */ -#define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER 0x00000624 /* TYPE_PHY_RECEIVE_FRAMING_ERROR_COUNTER Register */ -#define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD 0x00000628 /* TYPE_PHY_RECEIVE_ERROR_THRESHOLD Register */ -#define PCIE_PHY_PHY_TEST_CONTROL 0x0000062c /* TYPE_PHY_TEST_CONTROL Register */ -#define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE 0x00000630 /* TYPE_PHY_SERDES_CONTROL_OVERRIDE Register */ -#define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE 0x00000634 /* TYPE_PHY_TIMING_PARAMETER_OVERRIDE Register */ -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES 0x00000638 /* TYPE_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES Register */ -#define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES 0x0000063c /* TYPE_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES Register */ /**************************************************************************** @@ -281,60 +225,6 @@ /**************************************************************************** - * BCM70012_TGT_TOP_MDIO - ***************************************************************************/ -#define MDIO_CTRL0 0x00000730 /* PCIE Serdes MDIO Control Register 0 */ -#define MDIO_CTRL1 0x00000734 /* PCIE Serdes MDIO Control Register 1 */ -#define MDIO_CTRL2 0x00000738 /* PCIE Serdes MDIO Control Register 2 */ - - -/**************************************************************************** - * BCM70012_TGT_TOP_TGT_RGR_BRIDGE - ***************************************************************************/ -#define TGT_RGR_BRIDGE_REVISION 0x00000740 /* PCIE RGR Bridge Revision Register */ -#define TGT_RGR_BRIDGE_CTRL 0x00000744 /* RGR Bridge Control Register */ -#define TGT_RGR_BRIDGE_RBUS_TIMER 0x00000748 /* RGR Bridge RBUS Timer Register */ -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_0 0x0000074c /* RGR Bridge Spare Software Reset 0 Register */ -#define TGT_RGR_BRIDGE_SPARE_SW_RESET_1 0x00000750 /* RGR Bridge Spare Software Reset 1 Register */ - - -/**************************************************************************** - * BCM70012_I2C_TOP_I2C - ***************************************************************************/ -#define I2C_CHIP_ADDRESS 0x00000800 /* I2C Chip Address And Read/Write Control */ -#define I2C_DATA_IN0 0x00000804 /* I2C Write Data Byte 0 */ -#define I2C_DATA_IN1 0x00000808 /* I2C Write Data Byte 1 */ -#define I2C_DATA_IN2 0x0000080c /* I2C Write Data Byte 2 */ -#define I2C_DATA_IN3 0x00000810 /* I2C Write Data Byte 3 */ -#define I2C_DATA_IN4 0x00000814 /* I2C Write Data Byte 4 */ -#define I2C_DATA_IN5 0x00000818 /* I2C Write Data Byte 5 */ -#define I2C_DATA_IN6 0x0000081c /* I2C Write Data Byte 6 */ -#define I2C_DATA_IN7 0x00000820 /* I2C Write Data Byte 7 */ -#define I2C_CNT_REG 0x00000824 /* I2C Transfer Count Register */ -#define I2C_CTL_REG 0x00000828 /* I2C Control Register */ -#define I2C_IIC_ENABLE 0x0000082c /* I2C Read/Write Enable And Interrupt */ -#define I2C_DATA_OUT0 0x00000830 /* I2C Read Data Byte 0 */ -#define I2C_DATA_OUT1 0x00000834 /* I2C Read Data Byte 1 */ -#define I2C_DATA_OUT2 0x00000838 /* I2C Read Data Byte 2 */ -#define I2C_DATA_OUT3 0x0000083c /* I2C Read Data Byte 3 */ -#define I2C_DATA_OUT4 0x00000840 /* I2C Read Data Byte 4 */ -#define I2C_DATA_OUT5 0x00000844 /* I2C Read Data Byte 5 */ -#define I2C_DATA_OUT6 0x00000848 /* I2C Read Data Byte 6 */ -#define I2C_DATA_OUT7 0x0000084c /* I2C Read Data Byte 7 */ -#define I2C_CTLHI_REG 0x00000850 /* I2C Control Register */ -#define I2C_SCL_PARAM 0x00000854 /* I2C SCL Parameter Register */ - - -/**************************************************************************** - * BCM70012_I2C_TOP_I2C_GR_BRIDGE - ***************************************************************************/ -#define I2C_GR_BRIDGE_REVISION 0x00000be0 /* GR Bridge Revision */ -#define I2C_GR_BRIDGE_CTRL 0x00000be4 /* GR Bridge Control Register */ -#define I2C_GR_BRIDGE_SPARE_SW_RESET_0 0x00000be8 /* GR Bridge Software Reset 0 Register */ -#define I2C_GR_BRIDGE_SPARE_SW_RESET_1 0x00000bec /* GR Bridge Software Reset 1 Register */ - - -/**************************************************************************** * BCM70012_MISC_TOP_MISC1 ***************************************************************************/ #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0 0x00000c00 /* Tx DMA Descriptor List0 First Descriptor lower Address */ @@ -420,87 +310,6 @@ #define GISB_ARBITER_SCRATCH 0x00000f04 /* GISB ARBITER Scratch Register */ #define GISB_ARBITER_REQ_MASK 0x00000f08 /* GISB ARBITER Master Request Mask Register */ #define GISB_ARBITER_TIMER 0x00000f0c /* GISB ARBITER Timer Value Register */ -#define GISB_ARBITER_BP_CTRL 0x00000f10 /* GISB ARBITER Breakpoint Control Register */ -#define GISB_ARBITER_BP_CAP_CLR 0x00000f14 /* GISB ARBITER Breakpoint Capture Clear Register */ -#define GISB_ARBITER_BP_START_ADDR_0 0x00000f18 /* GISB ARBITER Breakpoint Start Address 0 Register */ -#define GISB_ARBITER_BP_END_ADDR_0 0x00000f1c /* GISB ARBITER Breakpoint End Address 0 Register */ -#define GISB_ARBITER_BP_READ_0 0x00000f20 /* GISB ARBITER Breakpoint Master Read Control 0 Register */ -#define GISB_ARBITER_BP_WRITE_0 0x00000f24 /* GISB ARBITER Breakpoint Master Write Control 0 Register */ -#define GISB_ARBITER_BP_ENABLE_0 0x00000f28 /* GISB ARBITER Breakpoint Enable 0 Register */ -#define GISB_ARBITER_BP_START_ADDR_1 0x00000f2c /* GISB ARBITER Breakpoint Start Address 1 Register */ -#define GISB_ARBITER_BP_END_ADDR_1 0x00000f30 /* GISB ARBITER Breakpoint End Address 1 Register */ -#define GISB_ARBITER_BP_READ_1 0x00000f34 /* GISB ARBITER Breakpoint Master Read Control 1 Register */ -#define GISB_ARBITER_BP_WRITE_1 0x00000f38 /* GISB ARBITER Breakpoint Master Write Control 1 Register */ -#define GISB_ARBITER_BP_ENABLE_1 0x00000f3c /* GISB ARBITER Breakpoint Enable 1 Register */ -#define GISB_ARBITER_BP_START_ADDR_2 0x00000f40 /* GISB ARBITER Breakpoint Start Address 2 Register */ -#define GISB_ARBITER_BP_END_ADDR_2 0x00000f44 /* GISB ARBITER Breakpoint End Address 2 Register */ -#define GISB_ARBITER_BP_READ_2 0x00000f48 /* GISB ARBITER Breakpoint Master Read Control 2 Register */ -#define GISB_ARBITER_BP_WRITE_2 0x00000f4c /* GISB ARBITER Breakpoint Master Write Control 2 Register */ -#define GISB_ARBITER_BP_ENABLE_2 0x00000f50 /* GISB ARBITER Breakpoint Enable 2 Register */ -#define GISB_ARBITER_BP_START_ADDR_3 0x00000f54 /* GISB ARBITER Breakpoint Start Address 3 Register */ -#define GISB_ARBITER_BP_END_ADDR_3 0x00000f58 /* GISB ARBITER Breakpoint End Address 3 Register */ -#define GISB_ARBITER_BP_READ_3 0x00000f5c /* GISB ARBITER Breakpoint Master Read Control 3 Register */ -#define GISB_ARBITER_BP_WRITE_3 0x00000f60 /* GISB ARBITER Breakpoint Master Write Control 3 Register */ -#define GISB_ARBITER_BP_ENABLE_3 0x00000f64 /* GISB ARBITER Breakpoint Enable 3 Register */ -#define GISB_ARBITER_BP_START_ADDR_4 0x00000f68 /* GISB ARBITER Breakpoint Start Address 4 Register */ -#define GISB_ARBITER_BP_END_ADDR_4 0x00000f6c /* GISB ARBITER Breakpoint End Address 4 Register */ -#define GISB_ARBITER_BP_READ_4 0x00000f70 /* GISB ARBITER Breakpoint Master Read Control 4 Register */ -#define GISB_ARBITER_BP_WRITE_4 0x00000f74 /* GISB ARBITER Breakpoint Master Write Control 4 Register */ -#define GISB_ARBITER_BP_ENABLE_4 0x00000f78 /* GISB ARBITER Breakpoint Enable 4 Register */ -#define GISB_ARBITER_BP_START_ADDR_5 0x00000f7c /* GISB ARBITER Breakpoint Start Address 5 Register */ -#define GISB_ARBITER_BP_END_ADDR_5 0x00000f80 /* GISB ARBITER Breakpoint End Address 5 Register */ -#define GISB_ARBITER_BP_READ_5 0x00000f84 /* GISB ARBITER Breakpoint Master Read Control 5 Register */ -#define GISB_ARBITER_BP_WRITE_5 0x00000f88 /* GISB ARBITER Breakpoint Master Write Control 5 Register */ -#define GISB_ARBITER_BP_ENABLE_5 0x00000f8c /* GISB ARBITER Breakpoint Enable 5 Register */ -#define GISB_ARBITER_BP_START_ADDR_6 0x00000f90 /* GISB ARBITER Breakpoint Start Address 6 Register */ -#define GISB_ARBITER_BP_END_ADDR_6 0x00000f94 /* GISB ARBITER Breakpoint End Address 6 Register */ -#define GISB_ARBITER_BP_READ_6 0x00000f98 /* GISB ARBITER Breakpoint Master Read Control 6 Register */ -#define GISB_ARBITER_BP_WRITE_6 0x00000f9c /* GISB ARBITER Breakpoint Master Write Control 6 Register */ -#define GISB_ARBITER_BP_ENABLE_6 0x00000fa0 /* GISB ARBITER Breakpoint Enable 6 Register */ -#define GISB_ARBITER_BP_START_ADDR_7 0x00000fa4 /* GISB ARBITER Breakpoint Start Address 7 Register */ -#define GISB_ARBITER_BP_END_ADDR_7 0x00000fa8 /* GISB ARBITER Breakpoint End Address 7 Register */ -#define GISB_ARBITER_BP_READ_7 0x00000fac /* GISB ARBITER Breakpoint Master Read Control 7 Register */ -#define GISB_ARBITER_BP_WRITE_7 0x00000fb0 /* GISB ARBITER Breakpoint Master Write Control 7 Register */ -#define GISB_ARBITER_BP_ENABLE_7 0x00000fb4 /* GISB ARBITER Breakpoint Enable 7 Register */ -#define GISB_ARBITER_BP_CAP_ADDR 0x00000fb8 /* GISB ARBITER Breakpoint Capture Address Register */ -#define GISB_ARBITER_BP_CAP_DATA 0x00000fbc /* GISB ARBITER Breakpoint Capture Data Register */ -#define GISB_ARBITER_BP_CAP_STATUS 0x00000fc0 /* GISB ARBITER Breakpoint Capture Status Register */ -#define GISB_ARBITER_BP_CAP_MASTER 0x00000fc4 /* GISB ARBITER Breakpoint Capture GISB MASTER Register */ -#define GISB_ARBITER_ERR_CAP_CLR 0x00000fc8 /* GISB ARBITER Error Capture Clear Register */ -#define GISB_ARBITER_ERR_CAP_ADDR 0x00000fcc /* GISB ARBITER Error Capture Address Register */ -#define GISB_ARBITER_ERR_CAP_DATA 0x00000fd0 /* GISB ARBITER Error Capture Data Register */ -#define GISB_ARBITER_ERR_CAP_STATUS 0x00000fd4 /* GISB ARBITER Error Capture Status Register */ -#define GISB_ARBITER_ERR_CAP_MASTER 0x00000fd8 /* GISB ARBITER Error Capture GISB MASTER Register */ - - -/**************************************************************************** - * BCM70012_MISC_TOP_MISC_GR_BRIDGE - ***************************************************************************/ -#define MISC_GR_BRIDGE_REVISION 0x00000fe0 /* GR Bridge Revision */ -#define MISC_GR_BRIDGE_CTRL 0x00000fe4 /* GR Bridge Control Register */ -#define MISC_GR_BRIDGE_SPARE_SW_RESET_0 0x00000fe8 /* GR Bridge Software Reset 0 Register */ -#define MISC_GR_BRIDGE_SPARE_SW_RESET_1 0x00000fec /* GR Bridge Software Reset 1 Register */ - - -/**************************************************************************** - * BCM70012_DBU_TOP_DBU - ***************************************************************************/ -#define DBU_DBU_CMD 0x00001000 /* DBU (Debug UART) command register */ -#define DBU_DBU_STATUS 0x00001004 /* DBU (Debug UART) status register */ -#define DBU_DBU_CONFIG 0x00001008 /* DBU (Debug UART) configuration register */ -#define DBU_DBU_TIMING 0x0000100c /* DBU (Debug UART) timing register */ -#define DBU_DBU_RXDATA 0x00001010 /* DBU (Debug UART) recieve data register */ -#define DBU_DBU_TXDATA 0x00001014 /* DBU (Debug UART) transmit data register */ - - -/**************************************************************************** - * BCM70012_DBU_TOP_DBU_RGR_BRIDGE - ***************************************************************************/ -#define DBU_RGR_BRIDGE_REVISION 0x000013e0 /* RGR Bridge Revision */ -#define DBU_RGR_BRIDGE_CTRL 0x000013e4 /* RGR Bridge Control Register */ -#define DBU_RGR_BRIDGE_RBUS_TIMER 0x000013e8 /* RGR Bridge RBUS Timer Register */ -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_0 0x000013ec /* RGR Bridge Software Reset 0 Register */ -#define DBU_RGR_BRIDGE_SPARE_SW_RESET_1 0x000013f0 /* RGR Bridge Software Reset 1 Register */ /**************************************************************************** @@ -533,15 +342,6 @@ /**************************************************************************** - * BCM70012_OTP_TOP_OTP_GR_BRIDGE - ***************************************************************************/ -#define OTP_GR_BRIDGE_REVISION 0x000017e0 /* GR Bridge Revision */ -#define OTP_GR_BRIDGE_CTRL 0x000017e4 /* GR Bridge Control Register */ -#define OTP_GR_BRIDGE_SPARE_SW_RESET_0 0x000017e8 /* GR Bridge Software Reset 0 Register */ -#define OTP_GR_BRIDGE_SPARE_SW_RESET_1 0x000017ec /* GR Bridge Software Reset 1 Register */ - - -/**************************************************************************** * BCM70012_AES_TOP_AES ***************************************************************************/ #define AES_CONFIG_INFO 0x00001800 /* AES Configuration Information Register */ @@ -555,16 +355,6 @@ /**************************************************************************** - * BCM70012_AES_TOP_AES_RGR_BRIDGE - ***************************************************************************/ -#define AES_RGR_BRIDGE_REVISION 0x00001be0 /* RGR Bridge Revision */ -#define AES_RGR_BRIDGE_CTRL 0x00001be4 /* RGR Bridge Control Register */ -#define AES_RGR_BRIDGE_RBUS_TIMER 0x00001be8 /* RGR Bridge RBUS Timer Register */ -#define AES_RGR_BRIDGE_SPARE_SW_RESET_0 0x00001bec /* RGR Bridge Software Reset 0 Register */ -#define AES_RGR_BRIDGE_SPARE_SW_RESET_1 0x00001bf0 /* RGR Bridge Software Reset 1 Register */ - - -/**************************************************************************** * BCM70012_DCI_TOP_DCI ***************************************************************************/ #define DCI_CMD 0x00001c00 /* DCI Command Register */ @@ -583,5276 +373,6 @@ /**************************************************************************** - * BCM70012_DCI_TOP_DCI_RGR_BRIDGE - ***************************************************************************/ -#define DCI_RGR_BRIDGE_REVISION 0x00001fe0 /* RGR Bridge Revision */ -#define DCI_RGR_BRIDGE_CTRL 0x00001fe4 /* RGR Bridge Control Register */ -#define DCI_RGR_BRIDGE_RBUS_TIMER 0x00001fe8 /* RGR Bridge RBUS Timer Register */ -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_0 0x00001fec /* RGR Bridge Software Reset 0 Register */ -#define DCI_RGR_BRIDGE_SPARE_SW_RESET_1 0x00001ff0 /* RGR Bridge Software Reset 1 Register */ - - -/**************************************************************************** - * BCM70012_CCE_TOP_CCE_RGR_BRIDGE - ***************************************************************************/ -#define CCE_RGR_BRIDGE_REVISION 0x000023e0 /* RGR Bridge Revision */ -#define CCE_RGR_BRIDGE_CTRL 0x000023e4 /* RGR Bridge Control Register */ -#define CCE_RGR_BRIDGE_RBUS_TIMER 0x000023e8 /* RGR Bridge RBUS Timer Register */ -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_0 0x000023ec /* RGR Bridge Software Reset 0 Register */ -#define CCE_RGR_BRIDGE_SPARE_SW_RESET_1 0x000023f0 /* RGR Bridge Software Reset 1 Register */ - - -/**************************************************************************** - * BCM70012_TGT_TOP_PCIE_CFG - ***************************************************************************/ -/**************************************************************************** - * PCIE_CFG :: DEVICE_VENDOR_ID - ***************************************************************************/ -/* PCIE_CFG :: DEVICE_VENDOR_ID :: DEVICE_ID [31:16] */ -#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_MASK 0xffff0000 -#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_ALIGN 0 -#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_BITS 16 -#define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_SHIFT 16 - -/* PCIE_CFG :: DEVICE_VENDOR_ID :: VENDOR_ID [15:00] */ -#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_MASK 0x0000ffff -#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_ALIGN 0 -#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_BITS 16 -#define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: STATUS_COMMAND - ***************************************************************************/ -/* PCIE_CFG :: STATUS_COMMAND :: DETECTED_PARITY_ERROR [31:31] */ -#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_MASK 0x80000000 -#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_SHIFT 31 - -/* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_SYSTEM_ERROR [30:30] */ -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_MASK 0x40000000 -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_SHIFT 30 - -/* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_MASTER_ABORT [29:29] */ -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_MASK 0x20000000 -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_SHIFT 29 - -/* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_TARGET_ABORT [28:28] */ -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_MASK 0x10000000 -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_SHIFT 28 - -/* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_TARGET_ABORT [27:27] */ -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_MASK 0x08000000 -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_SHIFT 27 - -/* PCIE_CFG :: STATUS_COMMAND :: DEVSEL_TIMING [26:25] */ -#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_MASK 0x06000000 -#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_BITS 2 -#define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_SHIFT 25 - -/* PCIE_CFG :: STATUS_COMMAND :: MASTER_DATA_PARITY_ERROR [24:24] */ -#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_MASK 0x01000000 -#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_SHIFT 24 - -/* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_CAPABLE [23:23] */ -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_MASK 0x00800000 -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_SHIFT 23 - -/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_0 [22:22] */ -#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_MASK 0x00400000 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_0_SHIFT 22 - -/* PCIE_CFG :: STATUS_COMMAND :: CAPABLE_66MHZ [21:21] */ -#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_MASK 0x00200000 -#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_SHIFT 21 - -/* PCIE_CFG :: STATUS_COMMAND :: CAPABILITIES_LIST [20:20] */ -#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_MASK 0x00100000 -#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_SHIFT 20 - -/* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_STATUS [19:19] */ -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_MASK 0x00080000 -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_SHIFT 19 - -/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_1 [18:16] */ -#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_MASK 0x00070000 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_BITS 3 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_1_SHIFT 16 - -/* PCIE_CFG :: STATUS_COMMAND :: RESERVED_2 [15:11] */ -#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_MASK 0x0000f800 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_BITS 5 -#define PCIE_CFG_STATUS_COMMAND_RESERVED_2_SHIFT 11 - -/* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_DISABLE [10:10] */ -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_MASK 0x00000400 -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_SHIFT 10 - -/* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_ENABLE [09:09] */ -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_MASK 0x00000200 -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_SHIFT 9 - -/* PCIE_CFG :: STATUS_COMMAND :: SYSTEM_ERROR_ENABLE [08:08] */ -#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_MASK 0x00000100 -#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_SHIFT 8 - -/* PCIE_CFG :: STATUS_COMMAND :: STEPPING_CONTROL [07:07] */ -#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_MASK 0x00000080 -#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_SHIFT 7 - -/* PCIE_CFG :: STATUS_COMMAND :: PARITY_ERROR_ENABLE [06:06] */ -#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_MASK 0x00000040 -#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_SHIFT 6 - -/* PCIE_CFG :: STATUS_COMMAND :: VGA_PALETTE_SNOOP [05:05] */ -#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_MASK 0x00000020 -#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_SHIFT 5 - -/* PCIE_CFG :: STATUS_COMMAND :: MEMORY_WRITE_AND_INVALIDATE [04:04] */ -#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_MASK 0x00000010 -#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_SHIFT 4 - -/* PCIE_CFG :: STATUS_COMMAND :: SPECIAL_CYCLES [03:03] */ -#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_MASK 0x00000008 -#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_SHIFT 3 - -/* PCIE_CFG :: STATUS_COMMAND :: BUS_MASTER [02:02] */ -#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_MASK 0x00000004 -#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_SHIFT 2 - -/* PCIE_CFG :: STATUS_COMMAND :: MEMORY_SPACE [01:01] */ -#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_MASK 0x00000002 -#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_SHIFT 1 - -/* PCIE_CFG :: STATUS_COMMAND :: I_O_SPACE [00:00] */ -#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_MASK 0x00000001 -#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_ALIGN 0 -#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_BITS 1 -#define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID - ***************************************************************************/ -/* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: PCI_CLASSCODE [31:08] */ -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_MASK 0xffffff00 -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_ALIGN 0 -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_BITS 24 -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_SHIFT 8 - -/* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: REVISION_ID [07:00] */ -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_MASK 0x000000ff -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_ALIGN 0 -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_BITS 8 -#define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE - ***************************************************************************/ -/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: BIST [31:24] */ -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_MASK 0xff000000 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_ALIGN 0 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_BITS 8 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_SHIFT 24 - -/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: HEADER_TYPE [23:16] */ -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_MASK 0x00ff0000 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_ALIGN 0 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_BITS 8 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_SHIFT 16 - -/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: LATENCY_TIMER [15:08] */ -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_MASK 0x0000ff00 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_ALIGN 0 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_BITS 8 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_SHIFT 8 - -/* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: CACHE_LINE_SIZE [07:00] */ -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_MASK 0x000000ff -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_ALIGN 0 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_BITS 8 -#define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: BASE_ADDRESS_1 - ***************************************************************************/ -/* PCIE_CFG :: BASE_ADDRESS_1 :: BASE_ADDRESS [31:16] */ -#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_MASK 0xffff0000 -#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_BITS 16 -#define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_SHIFT 16 - -/* PCIE_CFG :: BASE_ADDRESS_1 :: RESERVED_0 [15:04] */ -#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_MASK 0x0000fff0 -#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_BITS 12 -#define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_SHIFT 4 - -/* PCIE_CFG :: BASE_ADDRESS_1 :: PREFETCHABLE [03:03] */ -#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_MASK 0x00000008 -#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_BITS 1 -#define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_SHIFT 3 - -/* PCIE_CFG :: BASE_ADDRESS_1 :: TYPE [02:01] */ -#define PCIE_CFG_BASE_ADDRESS_1_TYPE_MASK 0x00000006 -#define PCIE_CFG_BASE_ADDRESS_1_TYPE_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_1_TYPE_BITS 2 -#define PCIE_CFG_BASE_ADDRESS_1_TYPE_SHIFT 1 - -/* PCIE_CFG :: BASE_ADDRESS_1 :: MEMORY_SPACE_INDICATOR [00:00] */ -#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_MASK 0x00000001 -#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_BITS 1 -#define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: BASE_ADDRESS_2 - ***************************************************************************/ -/* PCIE_CFG :: BASE_ADDRESS_2 :: EXTENDED_BASE_ADDRESS [31:00] */ -#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_MASK 0xffffffff -#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_BITS 32 -#define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: BASE_ADDRESS_3 - ***************************************************************************/ -/* PCIE_CFG :: BASE_ADDRESS_3 :: BASE_ADDRESS_2 [31:22] */ -#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_MASK 0xffc00000 -#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_BITS 10 -#define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_SHIFT 22 - -/* PCIE_CFG :: BASE_ADDRESS_3 :: RESERVED_0 [21:04] */ -#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_MASK 0x003ffff0 -#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_BITS 18 -#define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_SHIFT 4 - -/* PCIE_CFG :: BASE_ADDRESS_3 :: PREFETCHABLE [03:03] */ -#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_MASK 0x00000008 -#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_BITS 1 -#define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_SHIFT 3 - -/* PCIE_CFG :: BASE_ADDRESS_3 :: TYPE [02:01] */ -#define PCIE_CFG_BASE_ADDRESS_3_TYPE_MASK 0x00000006 -#define PCIE_CFG_BASE_ADDRESS_3_TYPE_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_3_TYPE_BITS 2 -#define PCIE_CFG_BASE_ADDRESS_3_TYPE_SHIFT 1 - -/* PCIE_CFG :: BASE_ADDRESS_3 :: MEMORY_SPACE_INDICATOR [00:00] */ -#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_MASK 0x00000001 -#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_BITS 1 -#define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: BASE_ADDRESS_4 - ***************************************************************************/ -/* PCIE_CFG :: BASE_ADDRESS_4 :: EXTENDED_BASE_ADDRESS_2 [31:00] */ -#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_MASK 0xffffffff -#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_ALIGN 0 -#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_BITS 32 -#define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: CARDBUS_CIS_POINTER - ***************************************************************************/ -/* PCIE_CFG :: CARDBUS_CIS_POINTER :: CARDBUS_CIS_POINTER [31:00] */ -#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_MASK 0xffffffff -#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_ALIGN 0 -#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_BITS 32 -#define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID - ***************************************************************************/ -/* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_DEVICE_ID [31:16] */ -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_MASK 0xffff0000 -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_ALIGN 0 -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_BITS 16 -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_SHIFT 16 - -/* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_VENDOR_ID [15:00] */ -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_MASK 0x0000ffff -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_ALIGN 0 -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_BITS 16 -#define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS - ***************************************************************************/ -/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_BASE_ADDRESS [31:16] */ -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_MASK 0xffff0000 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_ALIGN 0 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_BITS 16 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_SHIFT 16 - -/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_SIZE_INDICATION [15:11] */ -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_MASK 0x0000f800 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_ALIGN 0 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_BITS 5 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_SHIFT 11 - -/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: RESERVED_0 [10:01] */ -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_MASK 0x000007fe -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_ALIGN 0 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_BITS 10 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_SHIFT 1 - -/* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: EXPANSION_ROM_ENABLE [00:00] */ -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_MASK 0x00000001 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_ALIGN 0 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_BITS 1 -#define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: CAPABILITIES_POINTER - ***************************************************************************/ -/* PCIE_CFG :: CAPABILITIES_POINTER :: CAPABILITIES_POINTER [31:00] */ -#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_MASK 0xffffffff -#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_ALIGN 0 -#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_BITS 32 -#define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: INTERRUPT - ***************************************************************************/ -/* PCIE_CFG :: INTERRUPT :: RESERVED_0 [31:16] */ -#define PCIE_CFG_INTERRUPT_RESERVED_0_MASK 0xffff0000 -#define PCIE_CFG_INTERRUPT_RESERVED_0_ALIGN 0 -#define PCIE_CFG_INTERRUPT_RESERVED_0_BITS 16 -#define PCIE_CFG_INTERRUPT_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: INTERRUPT :: INTERRUPT_PIN [15:08] */ -#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_MASK 0x0000ff00 -#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_ALIGN 0 -#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_BITS 8 -#define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_SHIFT 8 - -/* PCIE_CFG :: INTERRUPT :: INTERRUPT_LINE [07:00] */ -#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_MASK 0x000000ff -#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_ALIGN 0 -#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_BITS 8 -#define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: VPD_CAPABILITIES - ***************************************************************************/ -/* PCIE_CFG :: VPD_CAPABILITIES :: RESERVED_0 [31:00] */ -#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_MASK 0xffffffff -#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_ALIGN 0 -#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_BITS 32 -#define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: VPD_DATA - ***************************************************************************/ -/* PCIE_CFG :: VPD_DATA :: RESERVED_0 [31:00] */ -#define PCIE_CFG_VPD_DATA_RESERVED_0_MASK 0xffffffff -#define PCIE_CFG_VPD_DATA_RESERVED_0_ALIGN 0 -#define PCIE_CFG_VPD_DATA_RESERVED_0_BITS 32 -#define PCIE_CFG_VPD_DATA_RESERVED_0_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY - ***************************************************************************/ -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_SUPPORT [31:27] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_MASK 0xf8000000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_BITS 5 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_SHIFT 27 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D2_SUPPORT [26:26] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_MASK 0x04000000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_SHIFT 26 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D1_SUPPORT [25:25] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_MASK 0x02000000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_SHIFT 25 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: AUX_CURRENT [24:22] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_MASK 0x01c00000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_BITS 3 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_SHIFT 22 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: DSI [21:21] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_MASK 0x00200000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_SHIFT 21 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: RESERVED_0 [20:20] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_MASK 0x00100000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_SHIFT 20 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_CLOCK [19:19] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_MASK 0x00080000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_SHIFT 19 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: VERSION [18:16] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_MASK 0x00070000 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_BITS 3 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_SHIFT 16 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: NEXT_POINTER [15:08] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_MASK 0x0000ff00 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_BITS 8 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_SHIFT 8 - -/* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: CAPABILITY_ID [07:00] */ -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_MASK 0x000000ff -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_BITS 8 -#define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS - ***************************************************************************/ -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PM_DATA [31:24] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_MASK 0xff000000 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_BITS 8 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_SHIFT 24 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_0 [23:16] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_MASK 0x00ff0000 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_BITS 8 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_STATUS [15:15] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_MASK 0x00008000 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_SHIFT 15 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SCALE [14:13] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_MASK 0x00006000 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_BITS 2 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_SHIFT 13 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SELECT [12:09] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_MASK 0x00001e00 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_BITS 4 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_SHIFT 9 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_ENABLE [08:08] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_MASK 0x00000100 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_SHIFT 8 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_1 [07:04] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_MASK 0x000000f0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_BITS 4 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_SHIFT 4 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: NO_SOFT_RESET [03:03] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_MASK 0x00000008 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_SHIFT 3 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_2 [02:02] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_MASK 0x00000004 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_BITS 1 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_SHIFT 2 - -/* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: POWER_STATE [01:00] */ -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_MASK 0x00000003 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_ALIGN 0 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_BITS 2 -#define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: MSI_CAPABILITY_HEADER - ***************************************************************************/ -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_CONTROL [31:24] */ -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_MASK 0xff000000 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_ALIGN 0 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_BITS 8 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_SHIFT 24 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: ADDRESS_CAPABLE_64_BIT [23:23] */ -#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_MASK 0x00800000 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_ALIGN 0 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_BITS 1 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_SHIFT 23 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_ENABLE [22:20] */ -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_MASK 0x00700000 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_ALIGN 0 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_BITS 3 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_SHIFT 20 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_CAPABLE [19:17] */ -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_MASK 0x000e0000 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_ALIGN 0 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_BITS 3 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_SHIFT 17 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_ENABLE [16:16] */ -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_MASK 0x00010000 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_ALIGN 0 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_BITS 1 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_SHIFT 16 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ -#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_ALIGN 0 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_BITS 8 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 - -/* PCIE_CFG :: MSI_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ -#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff -#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_ALIGN 0 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_BITS 8 -#define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: MSI_LOWER_ADDRESS - ***************************************************************************/ -/* PCIE_CFG :: MSI_LOWER_ADDRESS :: MSI_LOWER_ADDRESS [31:02] */ -#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_MASK 0xfffffffc -#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_ALIGN 0 -#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_BITS 30 -#define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_SHIFT 2 - -/* PCIE_CFG :: MSI_LOWER_ADDRESS :: RESERVED_0 [01:00] */ -#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_MASK 0x00000003 -#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_ALIGN 0 -#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_BITS 2 -#define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: MSI_UPPER_ADDRESS_REGISTER - ***************************************************************************/ -/* PCIE_CFG :: MSI_UPPER_ADDRESS_REGISTER :: MSI_UPPER_ADDRESS [31:00] */ -#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_MASK 0xffffffff -#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_ALIGN 0 -#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_BITS 32 -#define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: MSI_DATA - ***************************************************************************/ -/* PCIE_CFG :: MSI_DATA :: RESERVED_0 [31:16] */ -#define PCIE_CFG_MSI_DATA_RESERVED_0_MASK 0xffff0000 -#define PCIE_CFG_MSI_DATA_RESERVED_0_ALIGN 0 -#define PCIE_CFG_MSI_DATA_RESERVED_0_BITS 16 -#define PCIE_CFG_MSI_DATA_RESERVED_0_SHIFT 16 - -/* PCIE_CFG :: MSI_DATA :: MSI_DATA [15:00] */ -#define PCIE_CFG_MSI_DATA_MSI_DATA_MASK 0x0000ffff -#define PCIE_CFG_MSI_DATA_MSI_DATA_ALIGN 0 -#define PCIE_CFG_MSI_DATA_MSI_DATA_BITS 16 -#define PCIE_CFG_MSI_DATA_MSI_DATA_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER - ***************************************************************************/ -/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: RESERVED_0 [31:24] */ -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_MASK 0xff000000 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_ALIGN 0 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_BITS 8 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_SHIFT 24 - -/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: VENDOR_SPECIFIC_CAPABILITY_LENGTH [23:16] */ -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_MASK 0x00ff0000 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_ALIGN 0 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_BITS 8 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_SHIFT 16 - -/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_ALIGN 0 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_BITS 8 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 - -/* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_ALIGN 0 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_BITS 8 -#define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES - ***************************************************************************/ -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: POR_RESET_COUNTER [31:28] */ -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_MASK 0xf0000000 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_ALIGN 0 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_BITS 4 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_SHIFT 28 - -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: HOT_RESET_COUNTER [27:24] */ -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_MASK 0x0f000000 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_ALIGN 0 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_BITS 4 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_SHIFT 24 - -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: GRC_RESET_COUNTER [23:16] */ -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_MASK 0x00ff0000 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_ALIGN 0 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_BITS 8 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_SHIFT 16 - -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: PERST_RESET_COUNTER [15:08] */ -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_MASK 0x0000ff00 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_ALIGN 0 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_BITS 8 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_SHIFT 8 - -/* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: LINKDOWN_RESET_COUNTER [07:00] */ -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_MASK 0x000000ff -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_ALIGN 0 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_BITS 8 -#define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_SHIFT 0 - - -/**************************************************************************** - * PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL - ***************************************************************************/ -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: PRODUCT_ID [31:24] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xff000000 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_BITS 8 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 24 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ASIC_REVISION_ID [23:16] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_MASK 0x00ff0000 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_BITS 8 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_SHIFT 16 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TLP_MINOR_ERROR_TOLERANCE [15:15] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x00008000 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: LOG_HEADER_OVERFLOW [14:14] */ -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x00004000 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_ALIGN 0 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_BITS 1 -#define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14 - -/* PCIE_CFG :: MISCELLANEOUS_HOST_CONTR
