I think it would be much cleaner if we had a different function to handle wisoc reset instead of putting both on nic_reset. How about having a ath5k_hw_wisoc_reset This is wrong... #define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */ this bit was only available on earlier chips. To reset mac on later chips (WiSoC too) you need to use AR5K_RESET_CTL_PCU and we already do that below. This is something I have to clean up actually, bit 0 is reset mac (both PCU + DMA) ...

Or at least make them all ath5k_<bus type>_* eg ath5k_ahb_read_srev and ath5k_pci_read_srev, let's keep it clean... -- GPG ID: 0xD21DB2DB As you read this post global entropy rises. Have Fun ;-) Nick _______________________________________________ ath5k-devel mailing list ath5k-devel@lists.ath5k.org https://lists.ath5k.org/mailman/listinfo/ath5k-devel

Στις 26 Νοεμβρίου 2010 2:54 π.μ., ο χρήστης Jonathan Guerin When we convert to core clock units it's what we should do, all timings should change the same way. I don't know what this aPHY-RX-START-Delay is but if it changes that way we can use absolute values as we do for slot time and sifs. Maybe we can add a function ath5k_hw_get_default_ack_timeout that gets default sifs + default slot time + the needed aPHY-RX-START-Delay based on the standard (but what about turbo mode -40MHz-, do you think that ...