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V4L/DVB: mx1-camera: compile fix

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From: Linux Kernel Mailing List
Subject: V4L/DVB: mx1-camera: compile fix
Date: Friday, May 7, 2010 - 5:59 pm

Gitweb:     http://git.kernel.org/linus/b7d41d6d580743b1fed1b9560d948c9ef58564bd
Commit:     b7d41d6d580743b1fed1b9560d948c9ef58564bd
Parent:     6f550dc08369ee0bc6402963c377e65f0f2e3b71
Author:     Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
AuthorDate: Sat Mar 27 18:42:13 2010 -0300
Committer:  Mauro Carvalho Chehab <mchehab@redhat.com>
CommitDate: Thu May 6 19:20:51 2010 -0300

    V4L/DVB: mx1-camera: compile fix
    
    This fixes a regression of
    
    	7d58289 (mx1: prefix SOC specific defines with MX1_ and deprecate old names)
    
    Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
    Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
    Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
    Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
---
 arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h |    8 +++++++-
 drivers/media/video/mx1_camera.c             |    8 +++-----
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
index 07be8ad..7c4870b 100644
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
@@ -31,7 +31,13 @@
 #define DMA_MODE_WRITE		1
 #define DMA_MODE_MASK		1
 
-#define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR)
+#define MX1_DMA_REG(offset)	MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
+
+/* DMA Interrupt Mask Register */
+#define MX1_DMA_DIMR		MX1_DMA_REG(0x08)
+
+/* Channel Control Register */
+#define MX1_DMA_CCR(x)		MX1_DMA_REG(0x8c + ((x) << 6))
 
 #define IMX_DMA_MEMSIZE_32	(0 << 4)
 #define IMX_DMA_MEMSIZE_8	(1 << 4)
diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c
index 3c8ebfc..34a6601 100644
--- a/drivers/media/video/mx1_camera.c
+++ b/drivers/media/video/mx1_camera.c
@@ -49,8 +49,6 @@
 /*
  * CSI registers
  */
-#define DMA_CCR(x)	(0x8c + ((x) << 6))	/* Control Registers */
-#define DMA_DIMR	0x08			/* Interrupt ...
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