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perf, x86: Add Nehalem programming quirk to Westmere

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From: Linux Kernel Mailing List
Subject: perf, x86: Add Nehalem programming quirk to Westmere
Date: Tuesday, May 18, 2010 - 10:00 am

Gitweb:     http://git.kernel.org/linus/40b91cd10f000b4c4934e48e2e5c0bec66def144
Commit:     40b91cd10f000b4c4934e48e2e5c0bec66def144
Parent:     caaa8be3b6707cb9664e573a28b00f845ce9f32e
Author:     Peter Zijlstra <a.p.zijlstra@chello.nl>
AuthorDate: Mon Mar 29 16:37:17 2010 +0200
Committer:  Ingo Molnar <mingo@elte.hu>
CommitDate: Fri Apr 2 19:52:06 2010 +0200

    perf, x86: Add Nehalem programming quirk to Westmere
    
    According to the Xeon-5600 errata the Westmere suffers the same PMU
    programming bug as the original Nehalem did.
    
    Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
    LKML-Reference: <new-submission>
    Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
 arch/x86/kernel/cpu/perf_event_intel.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 1957e3f..f168b40 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -488,6 +488,7 @@ static void intel_pmu_enable_all(int added)
  * Workaround for:
  *   Intel Errata AAK100 (model 26)
  *   Intel Errata AAP53  (model 30)
+ *   Intel Errata BD53   (model 44)
  *
  * These chips need to be 'reset' when adding counters by programming
  * the magic three (non counting) events 0x4300D2, 0x4300B1 and 0x4300B5
@@ -980,6 +981,7 @@ static __init int intel_pmu_init(void)
 		intel_pmu_lbr_init_nhm();
 
 		x86_pmu.event_constraints = intel_westmere_event_constraints;
+		x86_pmu.enable_all = intel_pmu_nhm_enable_all;
 		pr_cont("Westmere events, ");
 		break;
 
--


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