Gitweb: http://git.kernel.org/linus/c1cc3db8e9fcf1c9d2db3f34552c73996d3d8a13
Commit: c1cc3db8e9fcf1c9d2db3f34552c73996d3d8a13
Parent: c9b870e7e796eea515a261a314917317ebb1cb4a
Author: Byungho Min <bhminjames@gmail.com>
AuthorDate: Tue Jun 23 21:39:56 2009 +0900
Committer: Ben Dooks <ben-linux@fluff.org>
CommitDate: Sun Aug 16 23:25:00 2009 +0100
ARM: S5PC100: Clock and PLL support
S5PC100 has 4 PLLs (APLL,MPLL,EPLL,HPLL) and 3 clock domains. Clock scheme is
implemented here.
Signed-off-by: Byungho Min <bhmin@samsung.com>
[ben-linux@fluff.org: edited title]
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
---
arch/arm/plat-s5pc1xx/include/plat/pll.h | 38 +
arch/arm/plat-s5pc1xx/include/plat/regs-clock.h | 421 +++++++++
arch/arm/plat-s5pc1xx/s5pc100-clock.c | 1139 +++++++++++++++++++++++
3 files changed, 1598 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-s5pc1xx/include/plat/pll.h b/arch/arm/plat-s5pc1xx/include/plat/pll.h
new file mode 100644
index 0000000..21afef1
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/pll.h
@@ -0,0 +1,38 @@
+/* arch/arm/plat-s5pc1xx/include/plat/pll.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ * Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX PLL code
+ *
+ * Based on plat-s3c64xx/include/plat/pll.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S5P_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
+#define S5P_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
+#define S5P_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
+#define S5P_PLL_MDIV_SHIFT (16)
+#define S5P_PLL_PDIV_SHIFT (8)
+#define S5P_PLL_SDIV_SHIFT (0)
+
+#include <asm/div64.h>
+
+static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk,
+ u32 pllcon)
+{
+ u32 mdiv, pdiv, sdiv;
+ u64 fvco = baseclk;
+
+ mdiv = (pllcon >> ...
