Author: Catalin Marinas <firstname.lastname@example.org>
AuthorDate: Thu Apr 30 17:06:09 2009 +0100
Committer: Russell King <email@example.com>
CommitDate: Thu Apr 30 20:12:50 2009 +0100
[ARM] 5487/1: ARM errata: Stale prediction on replaced interworking branch
This patch adds the workaround for the 430973 Cortex-A8 (r1p0..r1p2)
erratum. The BTAC/BTB is now flushed at every context switch.
Signed-off-by: Catalin Marinas <firstname.lastname@example.org>
Signed-off-by: Russell King <email@example.com>
arch/arm/Kconfig | 16 ++++++++++++++++
arch/arm/mm/proc-v7.S | 8 ++++++++
2 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e28a76b..84e4816 100644
@@ -749,6 +749,22 @@ config ARM_ERRATA_411920
It does not affect the MPCore. This option enables the ARM Ltd.
+ bool "ARM errata: Stale prediction on replaced interworking branch"
+ depends on CPU_V7
+ This option enables the workaround for the 430973 Cortex-A8
+ (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
+ interworking branch is replaced with another code sequence at the
+ same virtual address, whether due to self-modifying code or virtual
+ to physical address re-mapping, Cortex-A8 does not recover from the
+ stale interworking branch prediction. This results in Cortex-A8
+ executing the new code sequence in the incorrect ARM or Thumb state.
+ The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
+ and also flushes the branch target cache at every context switch.
+ Note that setting specific bits in the ACTLR register may not be
+ available in non-secure ...