Gitweb: http://git.kernel.org/linus/522b3d49179a0d2dc4e152b77eb82fbfe97782f4
Commit: 522b3d49179a0d2dc4e152b77eb82fbfe97782f4
Parent: 9242ef12f0d174da1739a071fb4a5fc5de27905e
Author: Greg Ungerer <gerg@uclinux.org>
AuthorDate: Tue Mar 24 17:33:41 2009 +1000
Committer: Greg Ungerer <gerg@uclinux.org>
CommitDate: Tue Mar 24 17:38:11 2009 +1000
m68knommu: fix 5407 ColdFire UART vector setup
There is a couple of problems with the UART vector setup for the 5307
ColdFire UART. The ICR register access should be 8bit, not 32bit. The
address of the UIVR register is wrong, it needs to be offset into the
MBAR register region. Fix these.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
---
arch/m68knommu/platform/5407/config.c | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/m68knommu/platform/5407/config.c b/arch/m68knommu/platform/5407/config.c
index 648b8b7..0ee8c1a 100644
--- a/arch/m68knommu/platform/5407/config.c
+++ b/arch/m68knommu/platform/5407/config.c
@@ -56,12 +56,12 @@ static struct platform_device *m5407_devices[] __initdata = {
static void __init m5407_uart_init_line(int line, int irq)
{
if (line == 0) {
- writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
- writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
+ writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
+ writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
} else if (line == 1) {
- writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
- writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
+ writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
+ writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
}
}
--
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