Gitweb: http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=7acab7...
Commit: 7acab7a9ca6b0c5b820f083424c57e6ac2031d9d
Parent: c18e99cfba746ab0ad8d45e1f351ed990947c58c
Author: Enrik Berkhan <Enrik.Berkhan@ge.com>
AuthorDate: Thu Mar 5 14:42:30 2009 +0800
Committer: Bryan Wu <cooloney@kernel.org>
CommitDate: Thu Mar 5 14:42:30 2009 +0800
Blackfin arch: fix bug - The SPORT_HYS bit is not set for BF561 0.5
IMHO the setting should depend on ANOMALY_05000305 which is about the
availability of the bit, not ANOMALY_05000265 which only describes the
SPORT sensitivity to noise (checked for BF561 only, though).
If that's not true for other BF variants, maybe the definition of
ANOMALY_05000265 for BF561 should be changed to '(1)' instead.
Signed-off-by: Enrik Berkhan <Enrik.Berkhan@ge.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
---
arch/blackfin/mach-common/clocks-init.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
index 9dddb6f..3539365 100644
--- a/arch/blackfin/mach-common/clocks-init.c
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -17,7 +17,7 @@
#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
#define PLL_CTL_VAL \
(((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
- (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0))
+ (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
__attribute__((l1_text))
static void do_sync(void)
--
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